Vivanco 10-100MB FAST ETHERNET SWITCH 5 PORTS - PROGRAMMING Specifikace Strana 52
- Strana / 82
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
DP83848C
,
DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015
www.ti.com
Table 6-9. Basic Mode Control Register (BMCR), address 0x00h (continued)
Bit Bit Name Default Description
8 DUPLEX MODE Strap, RW Duplex Mode:
When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be
selected.
1 = Full Duplex operation.
0 = Half Duplex operation.
7 COLLISION TEST 0, RW Collision Test:
1 = Collision test enabled.
0 = Normal operation.
When set, this bit will cause the COL signal to be asserted in response to the assertion of
TX_EN within 512-bit times. The COL signal will be deasserted within 4-bit times in
response to the deassertion of TX_EN.
6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0.
6.6.1.1.2 Basic Mode Status Register (BMSR)
Table 6-10. Basic Mode Status Register (BMSR), address 0x01h
Bit Bit Name Default Description
15 100BASE-T4 0, RO/P 100BASE-T4 Capable:
0 = Device not able to perform 100BASE-T4 mode.
14 100BASE-TX 1, RO/P 100BASE-TX Full Duplex Capable:
FULL DUPLEX 1 = Device able to perform 100BASE-TX in full duplex mode.
13 100BASE-TX 1, RO/P 100BASE-TX Half Duplex Capable:
HALF DUPLEX 1 = Device able to perform 100BASE-TX in half duplex mode.
12 10BASE-T 1, RO/P 10BASE-T Full Duplex Capable:
FULL DUPLEX 1 = Device able to perform 10BASE-T in full duplex mode.
11 10BASE-T 1, RO/P 10BASE-T Half Duplex Capable:
HALF DUPLEX 1 = Device able to perform 10BASE-T in half duplex mode.
10:7 RESERVED 0, RO RESERVED: Write as 0, read as 0.
6 MF PREAMBLE 1, RO/P Preamble suppression Capable:
SUPPRESSION 1 = Device able to perform management transaction with preamble suppressed, 32-bits of
preamble needed only once after reset, invalid opcode or invalid turnaround.
0 = Normal management operation.
5 AUTO-NEGOTIATION 0, RO Auto-Negotiation Complete:
COMPLETE
1 = Auto-Negotiation process complete.
0 = Auto-Negotiation process not complete.
4 REMOTE FAULT 0, RO/LH Remote Fault:
1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria:
NOTIFICATION from Link Partner of Remote Fault.
0 = No remote fault condition detected.
3 AUTO-NEGOTIATION 1, RO/P Auto Negotiation Ability:
ABILITY
1 = Device is able to perform Auto-Negotiation.
0 = Device is not able to perform Auto-Negotiation.
2 LINK STATUS 0, RO/LL Link Status:
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
The criteria for link validity is implementation specific. The occurrence of a link failure
condition will causes the Link Status bit to clear. Once cleared, this bit may only be set by
establishing a good link condition and a read through the management interface.
52 Detailed Description Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83848C DP83848I DP83848VYB DP83848YB
- Physical Layer Transceiver 1
- 1.4 Functional Block Diagram 2
- 3 Device Comparison 4
- 4.1 Pin Layout 5
- 4.2 Package Pin Assignments 6
- 4.4 Mac Data Interface 6
- 4.5 Clock Interface 7
- 4.6 LED Interface 8
- 4.8 Reset and Power Down 8
- 4.9 Strap Options 8
- 4.11 Special Connections 10
- 4.12 Power Supply Pins 10
- 5 Specifications 11
- 5.5 DC Specifications 12
- 5.6 AC Timing Requirements 13
- DP83848C 14
- DP83848I 14
- DP83848VYB, DP83848YB 14
- Specifications 17 17
- Submit Documentation Feedback 17
- Specifications 19 19
- Specifications 21 21
- Specifications 23 23
- 6 Detailed Description 26
- 6.2 Functional Block Diagram 27
- 6.3 Feature Description 28
- 6.3.1 Auto-Negotiation 28
- Detailed Description 29 29
- 6.3.2 Auto-MDIX 30
- 6.3.3 LED Interface 30
- 6.3.4 Internal Loopback 32
- 6.3.5 BIST 32
- 6.3.6 Energy Detect Mode 33
- 6.4 Device Functional Modes 33
- 6.4.1 MII Interface 33
- 6.4.2 Reduced MII Interface 34
- 6.4.5 PHY Address 36
- 6.4.7 Reset Operation 38
- 6.5 Programming 39
- 6.5.1 Architecture 39
- Detailed Description 41 41
- Detailed Description 43 43
- SD = (UD ⊕ N) (1) 44
- UD = (SD ⊕ N) (2) 44
- Detailed Description 45 45
- Detailed Description 47 47
- 6.6 Memory 48
- 6.6.1 Register Block 48
- Table 6-8. Register Table 49
- 7.1 Application Information 68
- 7.2 Typical Application 68
- 7.2.1 Design Requirements 68
- 7.2.3 Application Curves 75
- 7.3 Layout 76
- 7.3.1 Layout Guidelines 76
- 7.3.2 Layout Example 78
- PACKAGE OPTION ADDENDUM 80
- IMPORTANT NOTICE 82
Související produkty a manuály pro Síťové přepínače Vivanco 10-100MB FAST ETHERNET SWITCH 5 PORTS - PROGRAMMING
(6 stránky)
(12 stránky)Electrolux EBA60010X manuály
Uživatelské manuály a uživatelské příručky pro Konvice na kávu Electrolux EBA60010X.
Poskytujeme 4 manuály pdf Electrolux EBA60010X ke stažení zdarma podle typů dokumentů: Uživatelský manuál
Komentáře k této Příručce